A recirculating delay-locked loop (DLL) is becoming the system of choice for frequency synthesis where the output frequency is one to twenty times the input frequency. The recirculating delay-locked loop is more desirable than a traditional phase locked loop (PLL) because it provides a first order feedback system as opposed to the typical third or fourth order nature of a phase locked loop. In addition, a recirculating delay-locked loop has better long-term phase noise performance in comparison to a traditional phase locked loop. Furthermore, a delay-locked loop is easy to implement with a digital control that does not require a loop filter. An example recirculating delay-locked loop is described in A Portable Clock Multiplier Generator Using Digital CMOS Standard Cells, Michel Combes, Karim Dioury, and Alain Greiner, IEEE Journal of Solid-State Circuits, Vol. 31 No. 7, July, 1996.
A recirculating delay-locked loop utilizes a set of delay elements. The delay elements are adjusted to delay an output clock signal such that the output clock signal has a rising edge coincident with the rising edge of an input clock signal. By providing such delay mechanisms, the input and output clock signals are "locked" into phase with each other. Until an appropriate delay time is automatically determined by the recirculating delay-locked loop for a given input clock signal and output clock signal, any misalignment of phase of the input clock signal and the output clock signal is eliminated by aligning the rising edge of the output clock signal with the rising edge oof the input clock signal once for each clock signal of the input clock.